Analisis Ketahanan Kanal Samping Berbasis Waktu pada Algoritma Kriptografi RSA pada Mikrokontroler ESP32-S3
DOI:
https://doi.org/10.56706/ik.v20i2.145Keywords:
Serangan Kanal Samping, Analisis Waktu, RSA, ESP32, Kriptografi, Side-Channel Attack, Timing Analysis, CryptographyAbstract
Perkembangan pesat perangkat IoT meningkatkan adopsi algoritma RSA untuk mengamankan data. Namun, implementasi pada mikrokontroler rentan terhadap timing attack yang mengeksploitasi variasi durasi eksekusi untuk mengekstraksi kunci privat. Penelitian ini mengevaluasi ketahanan implementasi RSA 2048-bit pada mikrokontroler ESP32-S3 berbasis mbedTLS dengan hardware accelerator aktif melalui tiga skenario pengujian: rasio komputasi enkripsi-dekripsi, Test Vector Leakage Assessment (TVLA Fixed-vs-Random), dan sensitivitas bobot Hamming pada operasi raw modular exponentiation. Pengukuran waktu dilakukan pada register siklus clock CPU dengan resolusi 4,167 nanodetik (240 MHz) menggunakan interupsi terisolasi. Hasil menunjukkan waktu enkripsi rata-rata 2.275,00 μs (SD = 0,25 μs) dan dekripsi 275.400,00 μs (SD = 0,50 μs) dengan rasio 121:1. Uji TVLA menghasilkan |t|= 0.72 (p = 0,471), berada di bawah ambang batas kritis |t|< 4,5 dengan effect size Cohen's d = 0,032. Uji ANOVA (F = 1,04, p = 0,412) serta korelasi Pearson (r = -0,018) dan Spearman (p = -0,021) mengonfirmasi bahwa tidak terdapat ketergantungan waktu terhadap bobot input. Tidak ditemukan bukti statistik timing leakage pada implementasi ini, yang mengindikasikan bahwa modul akselerator perangkat keras ESP32-S3 efektif memitigasi serangan berbasis waktu pada skenario pengujian yang digunakan.
References
[1] R. Roman, J. Zhou, dan J. Lopez, "On the features and challenges of security and privacy in distributed internet of things," Computer Networks, vol. 57, no. 10, hal. 2266–2279, 2013. doi: 10.1016/j.comnet.2012.12.018.
[2] E. Barker, Q. Dang, et al., Recommendation for Key Management: Part 1 – General (Revised), NIST SP 800-57 Part 1 Rev. 5, National Institute of Standards and Technology, 2020.
[3] S. Kocher, J. Jaffe, B. Jun, dan P. Rohatgi, "Introduction to Differential Power Analysis," Journal of Cryptographic Engineering, vol. 1, no. 1, hal. 5–27, 2011. doi: 10.1007/s13389-011-0006-y.
[4] S. Mangard, E. Oswald, dan T. Popp, Power Analysis Attacks: Revealing the Secrets of Smart Cards. Springer, 2007. ISBN: 978-0-387-30857-9.
[5] P. C. Kocher, "Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems," dalam Advances in Cryptology — CRYPTO '96, Springer, 1996, hal. 104–113. doi: 10.1007/3-540-68697-5_9.
[6] D. Brumley dan D. Boneh, "Remote Timing Attacks are Practical," Computer Networks, vol. 48, no. 5, hal. 701–716, 2005. doi: 10.1016/j.comnet.2005.01.010.
[7] W. Schindler, "A Timing Attack against RSA with the Chinese Remainder Theorem," dalam Cryptographic Hardware and Embedded Systems — CHES 2000, Springer, 2000, hal. 109–124. doi: 10.1007/3-540-44499-8_8.
[8] Espressif Systems, ESP32-S3 Technical Reference Manual, Versi 1.2, 2023. [Daring]. Tersedia: https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf.
[9] J. Qiao, Performance Evaluation of Cryptographic Algorithms on ESP32 with Cryptographic Hardware Acceleration Feature, KTH Royal Institute of Technology, 2023.
[10] B. Köpf dan M. Dürmuth, "A Provably Secure and Efficient Countermeasure Against Timing Attacks," dalam 22nd IEEE Computer Security Foundations Symposium, IEEE, 2009, hal. 215–226. doi: 10.1109/CSF.2009.13.
[11] G. Goodwill, B. Jun, J. Jaffe, dan P. Rohatgi, "A Testing Methodology for Side-Channel Resistance Validation," dalam NIST Non-Invasive Attack Testing Workshop, 2011. [Daring]. Tersedia: https://csrc.nist.gov/csrc/media/events/non-invasive-attack-testing-workshop/documents/08_goodwill.pdf.
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